1. Field of the Invention
This invention is related to the field of processors and, more particularly, to address and operand sizes in processors.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Such processors may benefit from the large body of software written to the x86 architecture (since such processors may execute the software and thus computer systems employing the processors may enjoy increased acceptance in the market due to the large amount of available software).
As computer systems have continued to evolve, 64 bit address size (and sometimes operand size) has become desirable. A larger address size allows for programs having a larger memory footprint (the amount of memory occupied by the instructions in the program and the data operated upon by the program) to operate within the memory space. A larger operand size allows for operating upon larger operands, or for more precision in operands. More powerful applications and/or operating systems may be possible using 64 bit address and/or operand sizes.
Unfortunately, the x86 architecture is limited to a maximum 32 bit operand size and 32 bit address size. The operand size refers to the number of bits operated upon by the processor (e.g. the number of bits in a source or destination operand). The address size refers to the number of bits in an address generated by the processor. Thus, processors employing the x86 architecture may not serve the needs of applications which may benefit from 64 bit address or operand sizes.
The problems outlined above are in large part solved by a processor as described herein. The processor supports a processing mode in which the default address size is greater than 32 bits and the default operand size is 32 bits. The default address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the processing mode. The processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Additionally, an instruction prefix may be coded into an instruction to override the default address and/or operand size. Thus, an address size of 32 bits may be used when desired, and an operand size of 64 bits may be used when desired.
Broadly speaking, a processor is contemplated. The processor comprises a segment register, a control register, and an execution core. The segment register is configured to store a segment selector identifying a segment descriptor including a first operating mode indication and a second operating mode indication. The control register is configured to store an enable indication, wherein the processor is configured to establish a default operand size responsive to the enable indication, the first operating mode indication, and the second operating mode indication. The execution core is configured to execute an instruction having an instruction prefix which specifies that the default operand size be overridden with a different operand size.
Additionally, a processor is contemplated comprising a segment register, a control register, and an execution core. The segment register is configured to store a segment selector identifying a segment descriptor including a first operating mode indication and a second operating mode indication. The control register is configured to store an enable indication, wherein the processor is configured to establish a default address size responsive to the enable indication, the first operating mode indication, and the second operating mode indication. The execution core is configured to execute an instruction having an instruction prefix which specifies that the default address size be overridden with a different address size.
Still further, a method is contemplated. A default operand size is established in a processor in response to an enable indication in a control register within the processor and further in response to a first operating mode indication and a second operating mode indication in a segment descriptor. An instruction is executed which includes an instruction prefix which specifies that the default operand size be overridden by a different operand size. Operands of the different operand size are fetched during execution of the instruction.
Moreover, a method is contemplated. A default address size is established in a processor in response to an enable indication in a control register within the processor and further in response to a first operating mode indication and a second operating mode indication in a segment descriptor. An instruction is executed which includes an instruction prefix which specifies that the default address size be overridden by a different address size. Addresses of the different address size are generated during execution of the instruction.